The present application claims priority to Japanese Application No. P11-009683 filed Jan. 12, 1999, which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The invention relates to a semiconductor device having a conduction region made of polycrystal semiconductor and a gate electrode associated with the conduction region.
2. Description of the Related Art
In the related art, semiconductor devices such as a LSI (Large Scale Integrated circuit) are manufactured through forming transistors or other components directly on a single crystal silicon substrate. Since such semiconductor devices are formed on a single crystal substrate, the size thereof is limited to the wafer size. Moreover, they are fragile. Also, semiconductor devices as thus manufactured have limits in speed-up and voltage reduction through a scale-down, because of the junction capacitance of transistors.
In order to reduce the parasitic capacity of transistors, researches have been made on the technology for forming a semiconductor device on a SOI (Silicon on Insulator), or a substrate manufactured through forming a thin film of single crystal silicon on an insulating film. However, forming a single crystal thin film on an insulating film is difficult and thus SOIs are expensive. Also, since SOIs in development are manufactured by using wafers, it is not possible to obtain a semiconductor device of larger size than a wafer.
Researches have been also made on another technology for reducing the parasitic capacity of transistors through forming a semiconductor device on a thin film of polycrystal silicon which is formed on an insulating substrate. Polycrystal thin films can be formed on large substrates made of glass or other materials by the newest ELA (excimer laser annealing) (see Extended Abstracts of IC SSDM, p. 620, c1991, by T. Noguchi et al). It is therefore expected that the latter technology will achieve a system on panel, or a system having a LCD liquid crystal display) and a control LSI provided on one substrate (see NIKKEI MICRO DEVICE, February 1997, p. 90).
However, if a semiconductor device is manufactured by using polycrystal thin films, the conduction regions of transistors are made of polycrystal. This causes a problem of variations in characteristics due to grain boundary in the case of a scale-down of the conduction regions (see Jap. J. Appl. Phys., Vol. 32 (1993) L1584, by T. Noguchi). Due to the variations, the scaling law of MOS transistors can not be applied, just as it is, to semiconductor devices manufactured by using polycrystal thin films. Thus scale-down, i.e. speed-up and voltage reduction, of semiconductor devices becomes difficult.
The present invention has been made to overcome the above-described problems. It is an object of the invention to provide a semiconductor device in which variations in characteristics is reduced and thus speed-up and voltage reduction can be achieved.
A semiconductor device according to the present invention comprises a source and a drain provided apart from each other, a conduction region made of polycrystal semiconductor and provided next to both of the source and the drain, and a gate electrode associated with the conduction region, the gate length of the gate electrode being smaller than or equal to the average grain size of the conduction region, while the gate width of the gate electrode being greater than the average grain size of the conduction region.
In the semiconductor device according to the present invention, the gate length of the gate electrode is smaller than or equal to the average grain size of the conduction region, while the gate width is greater than the average grain size of the conduction region. Therefore, the semiconductor device exhibits the small range of variations in characteristics even if the gate length is reduced. As a result, speed-up and voltage reduction can be achieved.
Other and further objects, features and advantages of the invention will appear more fully from the following description.